New logic architectures for round robin arbitration and their automatic RTL generation

dc.contributor.author	Başkirt, Onur
dc.date.accessioned	2015-12-23T17:14:01Z
dc.date.available	2015-12-23T17:14:01Z
dc.date.issued	2008
dc.identifier.uri	http://hdl.handle.net/123456789/969
dc.language.iso	en	tr_TR
dc.publisher	Institute of Science	tr_TR
dc.subject	Integrated circuits_Design and construction	tr_TR
dc.subject	Computer architecture	tr_TR
dc.subject	Dissertations, Academic	tr_TR
dc.title	New logic architectures for round robin arbitration and their automatic RTL generation	tr_TR
dc.type	Thesis	tr_TR