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Publication Metadata only Grid resource discovery over distributed routers(2010) Kocak, Taskin; Lacks, Daniel; Kocak, Taskin, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, Turkey; Lacks, Daniel, College of Engineering and Computer Science, Orlando, United StatesComputational grids have emerged as a new paradigm for solving large complex problems over the recent years. The problem space and data set are divided into smaller pieces that are processed in parallel over the grid network and reassembled upon completion. Typically, resources are logged into a resource broker that is somewhat aware of all of the participants available on the grid. The resource broker scheme can be a bottleneck because of the amount of computational power and network bandwidth needed to maintain a fresh view of the grid. In this paper, we propose to place the load of managing the network resource discovery on to the network itself: inside of the routers. In the proposed protocol, the routers contain tables for resources similar to routing tables. These resource tables map IP addresses to the available computing resource values, which are provided through a scoring mechanism. Each resource provider is scored based on the attributes they provide such as the number of processors, processor frequency, amount of memory, hard drive space, and the network bandwidth. The resources are discovered on the grid by the protocol's discovery packets, which are encapsulated within the TCP/IP packets. The discovery packet visits the routers and look up in the resource tables until a satisfactory resource is found. The protocol is validated by simulations with five different deployment environments. ©2010 IEEE. © 2010 Elsevier B.V., All rights reserved.Publication Metadata only Exploiting the power of GPUs for multi-gigabit wireless baseband processing(2010) Kocak, Taskin; Hinitt, Nicholas; Kocak, Taskin, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, Turkey; Hinitt, Nicholas, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United KingdomIn this paper, we explore the feasibility of achieving gigabit baseband throughput using the vast computational power offered by the graphics processors (GPUs). One of the most computationally intensive functions commonly used in baseband communications, the Fast Fourier Transform (FFT) algorithm, is implemented on an NVIDIA GPU using their general-purpose computing platform called the Compute Unified Device Architecture (CUDA). The paper, first, investigates the implementation of an FFT algorithm using the GPU hardware and exploiting the computational capability available. It then outlines the limitations discovered and the methods used to overcome these challenges. Finally a new algorithm to compute FFT is proposed, which reduces interprocessor communication, and it is further optimized by improving memory access, enabling the processing rate to exceed 4 Gbps, achieving a processing time of a 512-point FFT in less than 200 ns. © 2010 IEEE. © 2010 Elsevier B.V., All rights reserved.Publication Metadata only On the performance of IEEE 802.15.3c millimeter-wave WPANs: PHY and MAC(2010) Zhu, Xiaoyi; Doufexi, Angela; Kocak, Taskin; Zhu, Xiaoyi, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United Kingdom; Doufexi, Angela, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United Kingdom; Kocak, Taskin, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United Kingdom, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, TurkeyThe large amount of unlicensed bandwidth available in the millimeter-wave has enabled very high data rate wireless applications. The IEEE 802.15 Task Group 3c has completed standardization efforts for multi-gigabit data rate communications on both the physical (PHY) and medium access control (MAC) layers. This paper presents a performance evaluation of the PHY and MAC layers of the newly published standard. Packet error rate (PER) and PHY throughput are simulated for different modes based on a typical 60 GHz channel model. The theoretical MAC throughput is calculated for different packet sizes and modes under different link conditions. The link adaptation mechanism is used to analyze the operating range versus data rate. The results show that very high data rates can be achieved over low distances. © 2010 IEEE. © 2010 Elsevier B.V., All rights reserved.Publication Metadata only Learning in the feed-forward random neural network: A critical review(2010) Georgiopoulos, Michael N.; Li, Cong; Kocak, Taskin; Georgiopoulos, Michael N., College of Engineering and Computer Science, Orlando, United States; Li, Cong, College of Engineering and Computer Science, Orlando, United States; Kocak, Taskin, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, TurkeyThe Random Neural Network (RNN) has received, since its inception in 1989, considerable attention and has been successfully used in a number of applications. In this critical review paper we focus on the feed-forward RNN model and its ability to solve classification problems. In particular, we paid special attention to the RNN literature related with learning algorithms that discover the RNN interconnection weights, suggested other potential algorithms that can be used to find the RNN interconnection weights, and compared the RNN model with other neural-network based and non-neural-network based classifier models. In review, the extensive literature review and experimentation with the RNN feed-forward model provided us with the necessary guidance to introduce six critical review comments that identify some gaps in the RNN related literature and suggest directions for future research. © 2011 Springer Science+Business Media B.V. © 2011 Elsevier B.V., All rights reserved.Publication Metadata only Beamforming performance analysis for OFDM based IEEE 802.11ad millimeter-wave WPANs(2011) Zhu, Xiaoyi; Doufexi, Angela; Kocak, Taskin; Zhu, Xiaoyi, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United Kingdom; Doufexi, Angela, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United Kingdom; Kocak, Taskin, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, TurkeyThis paper exploits the performance of three types of beamforming techniques over the 60 GHz orthogonal frequency division multiplexing (OFDM) based wireless personal area networks (WPANs). The effective SNR over typical IEEE 802.11ad channel models is used as the criterion to compare the beamforming performance. Symbol-wise beamforming reduces the complexity considerably compared to subcarrier-wise beamforming with some performance loss, while hybrid beamforming provides much less performance degradation at a reasonable cost. In order to verify the results, the bit error rate (BER) performance is simulated. In addition, the system throughput over range is presented in the paper. © 2011 IEEE. © 2013 Elsevier B.V., All rights reserved.Publication Metadata only Area efficient system-on-programmable-chip design for a wireless touch-triggered machining probe(2011) Mimis, Konstantinos; Kocak, Taskin; Mimis, Konstantinos, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United Kingdom; Kocak, Taskin, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, TurkeyIn this paper, we present the design and implementation details of a System-on-Programmable-Chip (SoPC), which replaces the circuitry that controls the operation of a touch-triggered machining probe with radio transmission capability. The probe is used to get precise measurements of three dimensional geometric parts. The goal is to achieve size reduction of an existing circuitry inside the probe, that consists of two microcontrollers and a reconfigurable hardware device such as a Field Programmable Gate Array (FPGA), that implements some custom functions. In order to reduce the printed circuit board (PCB) area occupied by these three chips and the associated routing area, we combine them on a single SoPC. An overall 6 fold reduction in PCB area occupied, corresponding to nearly 15cm2 is achieved. © 2011 IEEE. © 2011 Elsevier B.V., All rights reserved.Publication Metadata only A performance evaluation of 60 GHz MIMO systems for IEEE 802.11ad WPANs(2011) Zhu, Xiaoyi; Doufexi, Angela; Kocak, Taskin; Zhu, Xiaoyi, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United Kingdom; Doufexi, Angela, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United Kingdom; Kocak, Taskin, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, TurkeyThe IEEE 802.11ad task group has published its first draft to cope with the characteristics in 60 GHz millimeter-wave (mmWave) wireless communications. In this paper, three different 2x2 multiple-input multiple-output (MIMO) techniques are considered to enhance the performance of 60 GHz wireless personal networks (WPANs). Packet Error Rate (PER) and link throughput performance are simulated under different channel conditions. In addition, the system throughput over operation range is presented in the paper. Results show that significant enhancements in both coverage and capacity can be achieved by employing space-time block codes (STBC), spatial multiplexing (SM) and three different configurations of beamforming. © 2011 IEEE. © 2012 Elsevier B.V., All rights reserved.Publication Metadata only A performance enhancement for 60 GHz wireless indoor applications(2012) Zhu, Xiaoyi; Doufexi, Angela; Kocak, Taskin; Zhu, Xiaoyi, University of Bristol, Bristol, United Kingdom; Doufexi, Angela, University of Bristol, Bristol, United Kingdom; Kocak, Taskin, Bahçeşehir Üniversitesi, Istanbul, TurkeyThis paper studies the throughput and range of the OFDM based IEEE 802.11ad millimeter-wave WPANs. The cross layer results show that the MIMO and beamforming schemes with frame aggregation and block acknowledgement enhance the throughput and operation range compared to the case of single antenna with reasonable hardware complexity. © 2012 IEEE. © 2012 Elsevier B.V., All rights reserved.Publication Metadata only Reliable routing in wireless sensor networks for smart grid environments, Akilli şebeke ortaminda kablosuz algilayici aǧ teknolojisi ile güvenilir yönlendirme(2012) Şahin, Dilan; Bülbül, Şafak; Güngör, Vehbi Çağrı; Kocak, Taskin; Şahin, Dilan, Bahçeşehir Üniversitesi, Istanbul, Turkey; Bülbül, Şafak, Bahçeşehir Üniversitesi, Istanbul, Turkey; Güngör, Vehbi Çağrı, Bahçeşehir Üniversitesi, Istanbul, Turkey; Kocak, Taskin, Bahçeşehir Üniversitesi, Istanbul, TurkeyThe environmental conditions, e.g., fading, multi-path, obstructions, in smart grid environment, prevent reliable and successful packet transmissions for Wireless Sensor Network (WSN) technology. To provide reliable communications with WSN, to overcome the harsh environmental conditions of smart grid, and to prolong the network life time, reliable link quality estimation should be made and routing algorithms which consider multiple conditions, e.g., energy consumption, shortest path and link quality, should be used. In this paper, the performances of routing algorithms which can address this need are compared in terms of average delay, network lifetime and packet delivery rate in smart grid substation environment. Moreover, WSN-based smart grid applications and the challenges in estimation of link quality are briefly explained. © 2012 IEEE. © 2012 Elsevier B.V., All rights reserved.Publication Metadata only Design and implementation of high-performance high-valency ling adders(2012) Kocak, Taskin; Patil, Preeti; Kocak, Taskin, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, Turkey; Patil, Preeti, Department of Electrical and Electronic Engineering, University of Bristol, Bristol, United KingdomParallel prefix adders are used for efficient VLSI implementation of binary number additions. Ling architecture offers a faster carry computation stage compared to the conventional parallel prefix adders. Recently, Jackson and Talwar proposed a new method to factorize Ling adders, which helps to reduce the complexity as well as the delay of the adder further. This paper discusses the design and implementation details for such lower complexity, fast parallel prefix adders based on Ling theory of factorization. In particular, valency or radix, the number of inputs to a single node, is explored as a design parameter. Several low and high valency adders are implemented in 65 nm CMOS technology. Experimental results show that the high-valency Ling adders have superior area × delay characteristics over previously reported Ling-based or non-Ling adders for the same input size. Moreover, our 20-bit high valency adder has a better area × delay measurement than the previously-published 16-bit adders. © 2012 IEEE. © 2012 Elsevier B.V., All rights reserved.