Publication: GPU-Based Gigabit LDPC Decoder
| dc.contributor.author | Keskin, Selçuk | |
| dc.contributor.author | Kocak, Taskin | |
| dc.contributor.institution | Keskin, Selçuk, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, Turkey | |
| dc.contributor.institution | Kocak, Taskin, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, Turkey | |
| dc.date.accessioned | 2025-10-05T16:15:41Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | In this letter, we present design and implementation of a parallel software low-density parity-check (LDPC) decoding algorithm on graphics processing units (GPUs). As a solution for the LDPC decoder, dedicated application-specific integrated circuit or field programmable gate array implementations is proposed in recent years in order to support high throughput despite their long deployment cycle, high design, and especially fixed functionalities. On the other hand, the implementations on GPU as a software solution provide flexible, scalable, and less expensive solutions in a shorter deployment cycle. We present some GPU-based optimizations for a major LDPC decoder algorithm to obtain high throughput in digital communication systems. Experimental results demonstrate that the proposed LDPC decoder achieves more than 1.27 Gb/s peak throughput on a single GPU. © 2017 Elsevier B.V., All rights reserved. | |
| dc.identifier.doi | 10.1109/LCOMM.2017.2704113 | |
| dc.identifier.endpage | 1706 | |
| dc.identifier.issn | 10897798 | |
| dc.identifier.issue | 8 | |
| dc.identifier.scopus | 2-s2.0-85029597873 | |
| dc.identifier.startpage | 1703 | |
| dc.identifier.uri | https://doi.org/10.1109/LCOMM.2017.2704113 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.14719/12002 | |
| dc.identifier.volume | 21 | |
| dc.language.iso | en | |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | |
| dc.relation.source | IEEE Communications Letters | |
| dc.subject.authorkeywords | Concatenated Decoders | |
| dc.subject.authorkeywords | Cuda | |
| dc.subject.authorkeywords | Decoding | |
| dc.subject.authorkeywords | Gpu | |
| dc.subject.authorkeywords | High Throughput | |
| dc.subject.authorkeywords | Ldpc Codes | |
| dc.subject.authorkeywords | Msa | |
| dc.subject.authorkeywords | Computer Graphics | |
| dc.subject.authorkeywords | Concatenated Codes | |
| dc.subject.authorkeywords | Decoding | |
| dc.subject.authorkeywords | Digital Communication Systems | |
| dc.subject.authorkeywords | Field Programmable Gate Arrays (fpga) | |
| dc.subject.authorkeywords | Integrated Circuit Design | |
| dc.subject.authorkeywords | Optimization | |
| dc.subject.authorkeywords | Program Processors | |
| dc.subject.authorkeywords | Satellite Communication Systems | |
| dc.subject.authorkeywords | Throughput | |
| dc.subject.authorkeywords | Concatenated Decoders | |
| dc.subject.authorkeywords | Cuda | |
| dc.subject.authorkeywords | Design And Implementations | |
| dc.subject.authorkeywords | Field-programmable Gate Array Implementations | |
| dc.subject.authorkeywords | High Throughput | |
| dc.subject.authorkeywords | Ldpc Codes | |
| dc.subject.authorkeywords | Low Density Parity Check Decoding | |
| dc.subject.authorkeywords | Parallel Software | |
| dc.subject.authorkeywords | Graphics Processing Unit | |
| dc.subject.indexkeywords | Computer graphics | |
| dc.subject.indexkeywords | Concatenated codes | |
| dc.subject.indexkeywords | Decoding | |
| dc.subject.indexkeywords | Digital communication systems | |
| dc.subject.indexkeywords | Field programmable gate arrays (FPGA) | |
| dc.subject.indexkeywords | Integrated circuit design | |
| dc.subject.indexkeywords | Optimization | |
| dc.subject.indexkeywords | Program processors | |
| dc.subject.indexkeywords | Satellite communication systems | |
| dc.subject.indexkeywords | Throughput | |
| dc.subject.indexkeywords | concatenated decoders | |
| dc.subject.indexkeywords | CUDA | |
| dc.subject.indexkeywords | Design and implementations | |
| dc.subject.indexkeywords | Field-programmable gate array implementations | |
| dc.subject.indexkeywords | High throughput | |
| dc.subject.indexkeywords | LDPC codes | |
| dc.subject.indexkeywords | Low density parity check decoding | |
| dc.subject.indexkeywords | Parallel software | |
| dc.subject.indexkeywords | Graphics processing unit | |
| dc.title | GPU-Based Gigabit LDPC Decoder | |
| dc.type | Article | |
| dcterms.references | David J C MacKay, David J.C., Near Shannon limit performance of low density parity check codes, Electronics Letters, 32, 18, pp. 1645-1646, (1996), Tanner, R. Michael, A Recursive Approach to Low Complexity Codes, IEEE Transactions on Information Theory, 27, 5, pp. 533-547, (1981), Shih, Xin Yu, An 8.29 mm2 52 mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13 μm CMOS process, IEEE Journal of Solid-State Circuits, 43, 3, pp. 672-683, (2008), Understanding Belief Propagation and Its Generalizations, (2001), Cuda C Programming Guide, (2010), Duff, Iain S., Sparse matrix test problems, ACM Transactions on Mathematical Software, 15, 1, pp. 1-14, (1989), Kang, Soonyoung, Parallel LDPC decoder implementation on GPU based on unbalanced memory coalescing, Conference Record - International Conference on Communications, pp. 3692-3697, (2012), Hou, Yi, High throughput pipeline decoder for LDPC convolutional codes on GPU, IEEE Communications Letters, 19, 12, pp. 2066-2069, (2015), Falcão, Gabriel, Portable LDPC decoding on multicores using OpenCL [Applications Corner], IEEE Signal Processing Magazine, 29, 4, pp. 81-109, (2012), Wang, Guohui, High throughput low latency LDPC decoding on GPU for SDR systems, pp. 1258-1261, (2013) | |
| dspace.entity.type | Publication | |
| local.indexed.at | Scopus | |
| person.identifier.scopus-author-id | 56178510400 | |
| person.identifier.scopus-author-id | 7003330141 |
