Publication:
GPU-Based Gigabit LDPC Decoder

dc.contributor.authorKeskin, Selçuk
dc.contributor.authorKocak, Taskin
dc.contributor.institutionKeskin, Selçuk, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, Turkey
dc.contributor.institutionKocak, Taskin, Department of Computer Engineering, Bahçeşehir Üniversitesi, Istanbul, Turkey
dc.date.accessioned2025-10-05T16:15:41Z
dc.date.issued2017
dc.description.abstractIn this letter, we present design and implementation of a parallel software low-density parity-check (LDPC) decoding algorithm on graphics processing units (GPUs). As a solution for the LDPC decoder, dedicated application-specific integrated circuit or field programmable gate array implementations is proposed in recent years in order to support high throughput despite their long deployment cycle, high design, and especially fixed functionalities. On the other hand, the implementations on GPU as a software solution provide flexible, scalable, and less expensive solutions in a shorter deployment cycle. We present some GPU-based optimizations for a major LDPC decoder algorithm to obtain high throughput in digital communication systems. Experimental results demonstrate that the proposed LDPC decoder achieves more than 1.27 Gb/s peak throughput on a single GPU. © 2017 Elsevier B.V., All rights reserved.
dc.identifier.doi10.1109/LCOMM.2017.2704113
dc.identifier.endpage1706
dc.identifier.issn10897798
dc.identifier.issue8
dc.identifier.scopus2-s2.0-85029597873
dc.identifier.startpage1703
dc.identifier.urihttps://doi.org/10.1109/LCOMM.2017.2704113
dc.identifier.urihttps://hdl.handle.net/20.500.14719/12002
dc.identifier.volume21
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relation.sourceIEEE Communications Letters
dc.subject.authorkeywordsConcatenated Decoders
dc.subject.authorkeywordsCuda
dc.subject.authorkeywordsDecoding
dc.subject.authorkeywordsGpu
dc.subject.authorkeywordsHigh Throughput
dc.subject.authorkeywordsLdpc Codes
dc.subject.authorkeywordsMsa
dc.subject.authorkeywordsComputer Graphics
dc.subject.authorkeywordsConcatenated Codes
dc.subject.authorkeywordsDecoding
dc.subject.authorkeywordsDigital Communication Systems
dc.subject.authorkeywordsField Programmable Gate Arrays (fpga)
dc.subject.authorkeywordsIntegrated Circuit Design
dc.subject.authorkeywordsOptimization
dc.subject.authorkeywordsProgram Processors
dc.subject.authorkeywordsSatellite Communication Systems
dc.subject.authorkeywordsThroughput
dc.subject.authorkeywordsConcatenated Decoders
dc.subject.authorkeywordsCuda
dc.subject.authorkeywordsDesign And Implementations
dc.subject.authorkeywordsField-programmable Gate Array Implementations
dc.subject.authorkeywordsHigh Throughput
dc.subject.authorkeywordsLdpc Codes
dc.subject.authorkeywordsLow Density Parity Check Decoding
dc.subject.authorkeywordsParallel Software
dc.subject.authorkeywordsGraphics Processing Unit
dc.subject.indexkeywordsComputer graphics
dc.subject.indexkeywordsConcatenated codes
dc.subject.indexkeywordsDecoding
dc.subject.indexkeywordsDigital communication systems
dc.subject.indexkeywordsField programmable gate arrays (FPGA)
dc.subject.indexkeywordsIntegrated circuit design
dc.subject.indexkeywordsOptimization
dc.subject.indexkeywordsProgram processors
dc.subject.indexkeywordsSatellite communication systems
dc.subject.indexkeywordsThroughput
dc.subject.indexkeywordsconcatenated decoders
dc.subject.indexkeywordsCUDA
dc.subject.indexkeywordsDesign and implementations
dc.subject.indexkeywordsField-programmable gate array implementations
dc.subject.indexkeywordsHigh throughput
dc.subject.indexkeywordsLDPC codes
dc.subject.indexkeywordsLow density parity check decoding
dc.subject.indexkeywordsParallel software
dc.subject.indexkeywordsGraphics processing unit
dc.titleGPU-Based Gigabit LDPC Decoder
dc.typeArticle
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dspace.entity.typePublication
local.indexed.atScopus
person.identifier.scopus-author-id56178510400
person.identifier.scopus-author-id7003330141

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