Browsing by Author "Başaran, Ali"

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    GPF : Gigahertz Pulse Fitter
    (Bahçeşehir Üniversitesi Fen Bilimleri Enstitüsü, 2012-01) Başaran, Ali; Uğurdağ, H. Fatih
    High energy particle physics experiments require the processing of a superposition of signals from many particle detectors. Such signal contains many high frequency pulses, each of which belongs to a particle. The mathematical characteristics of a pulse, such as rise/fall times and amplitude, indicate the particle type. Processing of these signals on the fly, as they are received from detectors, is critical. Sending them to an array of hard disks to be processed later by a farm of computers would have multiple drawbacks. It would require too much bandwidth between the data acquisition cards and the storage array, too many disks, and too many computers so that they can keep up with the incoming data. Our solution to this problem is Gigahertz Pulse Fitter (GPF). GPF is a Data Acquisition System (DAQ) with a Field Programmable Gate Array (FPGA) next to Analog-to-Digital Converter (ADC). The FPGA processes the pulses as they occur and send only the pulse parameters to the storage/computer farm, thus enormously reducing bandwidth, storage, and compute requirements of the farm. This thesis outlines the design of GPF from concept to C code, from C code to SystemC code, from SystemC to HW architecture, from HW architecture to FPGA implementation. During this process, this thesis contributes in the following departments. It outlines a flow so that design verification stops being a moving target and the design works the first time it is programmed on the FPGA. It presents a novel architecture that combines pipelining and parallelism. The parallel part of the architecture is based on our concept of Optimized Performance Per Unit Block (OP-PUB). OP-PUB architecture is flexible and can be adapted to any pulse rate by calculating the necessary number of Identical Parallel Processors (IPPs) and FIFO sizes based on a formula. OP-PUB features a priority encoder based dispatcher at the top level and "Loop Pipelining" inside the IPPs. The IPP is a specialized CPU executing a fixed iteration body with an indeterminate number of iterations. On the FPGA implementation side, we use code generation techniques as well as smart pipelining and resource utilization. The architecture and design flow proposed are generic enough to withstand changes in the specifics of the curve fitting algorithms employed.