New logic architectures for round robin arbitration and their automatic RTL generation

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dc.contributor.authorBaşkirt, Onur
dc.date.accessioned2015-12-23T17:14:01Z
dc.date.available2015-12-23T17:14:01Z
dc.date.issued2008
dc.identifier.urihttp://hdl.handle.net/123456789/969
dc.language.isoentr_TR
dc.publisherInstitute of Sciencetr_TR
dc.subjectIntegrated circuits_Design and constructiontr_TR
dc.subjectComputer architecturetr_TR
dc.subjectDissertations, Academictr_TR
dc.titleNew logic architectures for round robin arbitration and their automatic RTL generationtr_TR
dc.typeThesistr_TR

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